Technical Projects

Topham: GPU Warp Scheduling for ML

C++, OpenCL, NumPy, PyTorch
Wrote library for core functions of BERT to test improvements for Vortex scheduler.

PIPELINED RISC-V CPU ON FPGA

Verilog and Xilinx Vivado
Designed, implemented, and ran a three-stage pipelined RISCV processor on a Xilinx PYNQ-Z1 FPGA complete with forwarding that eliminates stalling from all data hazards. In addition, the processor included an extension for Pointer Authentication Codes.s

MAPREDUCE

Rust
Implementented fault tolerant programming model for scalable and highly parallelized data processing based on the Google paper of the same name.

END-TO-END ENCRYPTED FILE SHARING SYSTEM

GOLang
Designed and implemented an end-to-end encrypted file-sharing system that supports storing, loading, and efficiently modifying files, all in conjunction with handling user permissions.